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Altera_Forum's avatar
Altera_Forum
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13 years ago

device to use in quartus

hiii, can any one suggest me a device that can handle large number of I/O buffers........

thank you................

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    First of you need to specify the Family you want to target and the speed grade you need.

    Then you might get suggestions and what are the IO count.
  • Altera_Forum's avatar
    Altera_Forum
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    first here i don't have conditions to use particular device, and here the IO count is 2410...

    thank you.....
  • Altera_Forum's avatar
    Altera_Forum
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    Well 2410??

    In that case there is no device with altera that has this much pin count.

    But , There is a work around.

    Are you using interfaces as the pins??

    Well you can set virtual pin assignment to the pins which you think wont be necessary as it might be integrated to other modules.

    The tool will reduce the pin count.

    But dont assign virtual pins to clocks ,resets or any serial buses.

    GOOD LUCK
  • Altera_Forum's avatar
    Altera_Forum
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    thank you very much,,,,,,now i allotted many interfaces to virtual pin assignment....so i managed to minimum number of IO buffers...........

  • Altera_Forum's avatar
    Altera_Forum
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    Well still how did you slected your device..

    Look Stratix 1-5 are high quality devices and will provide you with excellent timing, whereas ARRIA series is a medium quality device and the timing would be slightly pessimistic.

    So it depends on what the requirement is.

    GOOD LUCK
  • Altera_Forum's avatar
    Altera_Forum
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    fine thank you, ha yes you are right...... im already using startix family

  • Altera_Forum's avatar
    Altera_Forum
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    Oh then its ok..be sure to add the timing constraints through the sdc, otherwise you will only be compiling the design whereas timing analysis wont be done.

    GOOD LUCK
  • Altera_Forum's avatar
    Altera_Forum
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    IF you truly need 2400+ I/O, the use of a CPLD as an I/O expander in conjunction with an FPGA(s) would be advisable. Something like 2-3 484 FBGA Cyclone devices, and several Max II CPLD's. -James

  • Altera_Forum's avatar
    Altera_Forum
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    thank you...here actually i'm getting warnings like "timing requirements are not meet" can you please explain me to overcome these type of warnings,its true here actually i don't know how to add sdc file please solve this one too. once again thank you.......