Honored ContributorI am having trouble finding the pinout for the EP3C5E144C7N so I can try and build a board with a JTAG header. Does anyone know the proper pinout and connections to design a JTAG header on a EP3C5E144C7N ?
Honored ContributorYou can find the pinouts here (http://www.altera.com/literature/lit-dp.jsp?category=cyc%203&showspreadsheet=y). The configuration chapter (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf) in the handbook should give you all the information you need on how to make your jtag interface.
Honored Contributorok im looking at the way its routed and basically it requires a 4 layer board ?
Honored Contributoralso are there any dedicated ide controllers that use LVDS ? I like the idea of a ide controller that has its own sdram like the one mentioned
Honored ContributorYou'll have a real hard time designing it on a 4 layer board in my opinion. You have several power supplies to give to the FPGA, and should to it through proper planes to have a good decoupling. I'd recommend 8 layers as a strict minimum, and maybe 6 once you have a strong experience in designs with those FPGA and don't have to many I/O to route to and from the FPGA. In my company we typically design 10-12 layer boards.
IDE doesn't use LVDS, it's either LVCMOS or LVTTL signals. I don't understand what you mean by controller with its own sdram. Most IDE controllers une DMA to read/write into a memory shared with a CPU. The RAM isn't dedicated to the controller.Honored ContributorI've done a project with a pic microchip using pata hard drives, You must be right about the memory being shared by the controller and cpu, it says on the diagram "dual port ram" but in the diagram it only went to the Ata controller, In your opinion do i need an ata controller or is the cyclone III fast enough regardless of io voltage levels ?
Honored ContributorYou don't need any external ata controller if that's what you mean. Any IDE IP will fit in a Cyclone III and it's I/O are able to sustain the highest PATA speeds.
Honored ContributorThanks ! I've seen IP used alot and im not sure what it means exactly. could you clarify this for me ?
Honored ContributorI've got the pata port all routed out in altium designer, using bank 4+3 , the problem im having is trying to decide to do JTAG , AS, or PS programming on the board and which way will be easiest to do on the top of a one sided one layer board , I havent figured out how to make copper pads to place jumper wires on yet, im gonna try and figure out which way is easiest , what mode do you prefer ?
Honored ContributorHonored ContributorI forgot to say, use AS config, programming the config device via Jtag indirect programming.
This minimises the length of tracks to the config device/ JTAG header which maximises the chances of things working. Keep the distances from the FPGA to both these fairly short. Nial
