Designing a SPI slave

Just an update, looks like this issue is being caused by noise. If I simply unplug a flat cable from my Cyclone IV development board that connects 10 outputs to some buffers/drivers, the problem stops. The I/Os feeding this cable carry ~5MHz signals, including CLK, Latch & 6-bit Data.

I think your mistake is using the SPI clock as an actual clock in the design. Use a clock from the PLL as the clock to your module (and entire FPGA design if possible). This should be much faster than the SPI clock. Run the SPI clock through 2 registers to synchronize it to the FPGA clock. After that, run it to your SPI slave. Compare the SPI clock state to the previous state to detect rising or falling edges. Only sample the SPI clock on FPGA clock rising edges.

Thanks. I'll try that and post the results here. Its strange, though, because I've seen SPI examples in VHDL for FPGAs that simply have an "IF rising_edge(SPI_CLK) THEN..." inside, and without sync with any other clock. And I've done this using an old Lattice and Cypress CPLDs in the past. It's just this FPGA that's giving me trouble.

My development board has a 50MHz oscillator at PIN 25 of the Cyclone IV FPGA. I'm simply creating a signal called clk: in std_logic; , using process (clk) and placing if rising_edge(clk) then inside it. Then, under Assignments/Pin Planner, I'm assigning the CLK input to PIN_25 with I/O standard 3.3-V LVTTL. Since I don't want to modify the clock frequency, I assume I don't need to use a PLL. Am I doing this right?

By the way, I've implemented the SPI using the main FPGA clock: I have the SPI_CS, SPI_CLK and SPI_MOSI input signals from the main CPU that's sending SPI data to the FPGA (no synchronize register chain yet), and I've created the LAST_SPI_CS and LAST_SPI_CLK boolean variables, which contains the state of SPI_CS and SPI_CLK on the previous CLK edge (main FPGA clock). So, when SPI_CLK='1' and LAST_SPI_CLK='0' (while SPI_CS='0'), I'll sample SPI_MOSI and shift it into the array (spi_in<=spi_in(13 downto 0) & spi_mosi;). If SPI_CS goes high, I'll then process the received data in the SPI_IN array.

A better way to clarify what you are doing would be to post the actual code.

Well, I've removed the non-SPI related code, otherwise it'd be too big.

ENTITY Video IS
    PORT (CLK        : IN STD_LOGIC;    -- Main FPGA clock (50MHz XTAL). It's set on the Pin Planner as simply 3.3-V LVTTL / 8mA. Placed on a clock input pin
            SPI_CS    : IN STD_LOGIC;
            SPI_CLK    : IN STD_LOGIC;
            SPI_MOSI    : IN STD_LOGIC);
END Video;
ARCHITECTURE Refresh OF Video IS
        
    signal    SPI_IN            : STD_LOGIC_VECTOR (14 DOWNTO 0); -- Received SPI data is shifted here, MSB first
    signal    SPI_CLK_LAST        : STD_LOGIC :='0';
    signal    SPI_CS_LAST        : STD_LOGIC :='0';
            
BEGIN
   PROCESS (CLK) 
--    variable CLKCNT : integer :=0;        -- This is used to lower the SPI sampling rate vs. main clock
   BEGIN
    IF rising_edge(CLK) THEN
--    IF CLKCNT=5 then                -- This is used to lower the SPI sampling rate vs. main clock. With this uncommented, the SPI slave
--        CLKCNT:=0;                   -- works much better, but it's still losing a lot of data/edges.
        IF SPI_CS='0' THEN
                        
            IF SPI_CS_LAST='1' THEN
                -- (Some debug code would also go here. Thus this IF.)
                SPI_CS_LAST<='0'; 
            end if;
                                
            if SPI_CLK='1' and SPI_CLK_LAST='0' then
                SPI_CLK_LAST<='1';
                SPI_IN<=SPI_IN(13 downto 0) & SPI_MOSI;
            elsif SPI_CLK='0' then
                SPI_CLK_LAST<='0';                
            end if;
            
        ELSIF SPI_CS='1' and SPI_CS_LAST='0' THEN
            SPI_CS_LAST<='1';
            -- Here I'll process the data received in SPI_IN
        END IF;
        
--    ELSE                            -- This is used to lower the SPI sampling rate vs. main clock
--        CLKCNT:=CLKCNT+1;
--    END IF;
   END IF;
                        
   END PROCESS;

Well, I checked and my CLK is indeed being routed thru GCLK3; a global clock. So that's probably not the problem.

ENTITY Video IS
    PORT (  CLK       : IN STD_LOGIC;    -- Main FPGA clock (50MHz XTAL). It's set on the Pin Planner as simply 3.3-V LVTTL / 8mA. Placed on a clock input pin
            SPI_CS    : IN STD_LOGIC;
            SPI_CLK   : IN STD_LOGIC;
            SPI_MOSI  : IN STD_LOGIC;
            LEDS      : OUT STD_LOGIC_VECTOR(7 downto 0));    -- LEDS on the development board
END Video;
ARCHITECTURE Refresh OF Video IS
        
    signal    SPI_IN             : STD_LOGIC_VECTOR (14 DOWNTO 0); -- Received SPI data is shifted here, MSB first
    signal    SPI_CLK_LAST       : STD_LOGIC :='0';
    signal    SPI_CS_LAST        : STD_LOGIC :='0';
            
BEGIN
   PROCESS (CLK) 
   BEGIN
    IF rising_edge(CLK) THEN
        IF SPI_CS='0' THEN
                        
            IF SPI_CS_LAST='1' THEN
                SPI_IN_CNT<="00000000";
                SPI_CS_LAST<='0'; 
            end if;
                                
            if SPI_CLK='1' and SPI_CLK_LAST='0' then
                SPI_CLK_LAST<='1';
                SPI_IN<=SPI_IN(13 downto 0) & SPI_MOSI;
                SPI_IN_CNT<=SPI_IN_CNT+1;	
            elsif SPI_CLK='0' then
                SPI_CLK_LAST<='0';                
            end if;
            
        ELSIF SPI_CS='1' and SPI_CS_LAST='0' THEN
            SPI_CS_LAST<='1';
            -- Here I'll process the data received in SPI_IN
            LEDS<=SPI_IN_CNT;
        END IF;
    END IF;
                        
   END PROCESS;