Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Design Size and the timing accuracy

Dear Sir, I've met one problem. It is about the design size and timing accuracy. If I have a design which used up the FPGA 95% or above LEs, is it going to have some I/Os having worse tim...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Dear GPK,

Thanks for your explaination. The problem was found in a project which uses a FPGA MAXII micro to drive an external a LCM through an I2C interface designed via the I/Os. I've tried several times. When the design size larger,

the timing of output signal is going to be wrong. For some test pins, even

the outputs are incorrect. I feel strange. Thus, I think the problems were

caused by the limited resource in the FPGA.

:)

Regards,

Peter Chang