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Altera_Forum
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14 years ago

Design Size and the timing accuracy

Dear Sir, I've met one problem. It is about the design size and timing accuracy. If I have a design which used up the FPGA 95% or above LEs, is it going to have some I/Os having worse tim...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Dear GPK,

Thanks for your comment. I believe SDC is important for the timing constraints. However, is it possible that the requirements of my design

are over that FPGA could provide in timing, especially while the available

LEs are less.

Regards,

Peter Chang

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Hi Peter,

of course it could be more difficult for Quartus to implement your design when the uitilization is high. You mentioned that you have mainly I/O timing problems. Can you

explain it a little bit more ? Maybe I would help when you register your inputs and outputs

by using the registers in the I/O cells.

Kind regards

GPK