Design Size and the timing accuracy

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Dear Sir,

I've met one problem. It is about the design size and timing accuracy.

If I have a design which used up the FPGA 95% or above LEs, is it

going to have some I/Os having worse timing which may violate the requirements? Suppose, the answer is 'yes', because it is limited

by the available resources. What I am going to ask is how to efficiently

manage the available LEs to meet the requirements? Is setting timing

constraints in SDC file a goody way? In a case of no improvement, after

changing the contraints, does it mean the available resource and path

is used up? Thank you in advance.

Regards,

Peter Chang

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HI Peter,

at first you need a proper SDC file. You have at least to constrain you Inputs, Outputs and clocks. This is important, because the constrains are used by Quartus for implementation of your design.

Kind regards

GPK