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Altera_Forum
Honored Contributor
Honored Contributordesign simulation
hello i've done a design using quartus 17.1 pro. but i coudn't simulate this design. i tried to convert it to a VHDL script but i dindn't know how how can i simulate it or convert it
Altera_ForumHonored Contributor
Honored Contributorno i can't simulate using vwf and it isn't simple design it contains ip's like pll .transceiver ..
