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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

design simulation

hello i've done a design using quartus 17.1 pro. but i coudn't simulate this design. i tried to convert it to a VHDL script but i dindn't know how how can i simulate it or convert it
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

1.Attache the ERROR message/Log file.

2.Which IP's are used in the design?

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)