Altera_Forum
Honored Contributor
16 years agoDesign of controller with DDR2 hi-speed interface and NIOS CPU
http://inlinethumb31.webshots.com/45854/2456230460103611618S600x600Q85.jpg
Hello. We are now designing new system based on Stratix III. This is the first time I will use NIOS II processor and SOPC builder. Concept scheme of the system part is presenting on the picture. On the first (high-speed) stage data from ADC must be captured by ADC controlled and saved in DDR2 RAM. On the second (slow-speed) stage, data from DDR2 memory must be read by NIOS II and after making some calculations must be written back to the memory or transmitted out by slow-speed interface. The question is: 1. What component of SOPC builder should be in a place of block, which is marking by “yellow ?” ? 2. Also, I don’t understand, how could I link DDR2 256 bit local interface with 32 bit NIOS II interface. I think it must be some kind of Avalon bridge or adapter, but I couldn’t find information, concerning linking two SOPC devices with different bus width. Please, answer me or point me on documentation, where I can find solving for my problem. Thanks a lot.