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since your last post is a bit older, did you realized the BERT in FPGA?
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If I recall correctly, the BERT function in the Stratix IV series is hard-coded, i.e., you synthesize for the BERT or you synthesize for a design that uses the transceivers. The idea of using a BERT created in the fabric is that you can dynamically switch to it and then over to your transcieiver logic.
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Did you get the VHDL sources you mentioned in your first post of these thread?
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I wrote up a couple of articles on how to use the Altera Transceiver Toolkit ... it is quite buggy, so the articles are useful for figuring out that you are not going crazy, that in fact Altera provides broken software :)
The articles are near the top of this page:
https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html Cheers,
Dave
Honored Contributor
