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Altera_Forum
Honored Contributor
Honored ContributorDesign of an FPGA based bit error rate tester
Hello. I am looking into making an FPGA based BERT for some lab testing based on this article http://www.physics.smu.edu/web/research/preprints/smu-hep-11-14.pdf I found on the web. I am not an FPGA ...
Altera_ForumHonored Contributor
Honored ContributorHi,
since your last post is a bit older, did you realized the BERT in FPGA? Did you get the VHDL sources you mentioned in your first post of these thread?
