Design of an FPGA based bit error rate tester

Dave ,

Thank you. It would be very helpful if you could offer suggestions to me for this application. My application would be bit error rate testing of what are essentially SFP / SFP+ modules operating from 1.25Gbps to 10.3125Gbps. I need an electrical transmit and receive channel (SMA connections), an optical transmit and receive channel (SFP module), and a trigger output (SMA connection) for a scope. I certainly wouldn't argue with the option of having more I/O channels for future expansion but that is all I need at the moment. Ideally it would be able to run PRBS patterns and short user defined patterns (4-8 bits is enough to just basically do a 0001 pattern as a sanity check for proper data polarity). Is the transceiver toolkit user friendly? I have little experience with FPGA programming so that is why I was looking for some type of open source software or at least an interface that I could learn without needing years of FPGA experience. I have some Labview experience that allows me to toy with programs but again I am not an expert by any stretch of the word.

Thanks