Design Issue when FPGA is configured from serial flash

Thanks again guys for fantastic comments. This forum is awesome. yes indeed that was the problem. I have different critical interrupts which should be handled and it seems printf when the jtag is not active and design is in release mode causes major delays and therefore we end up interrupt starvation in the system. I will leave the system to function today over the night to 100% make sure that was the problem. We designed a system couple of months ago and strangely Master system stopped functioning. it was strange as battery monitor unit showed that battery was fine. I think this was the problem and we will try to update the firmware. Thanks again for fantastic comments as it saves me lots of time and I don't know why I forgot disabling all debug command this time. so the lessons learned and the most important one is DON't START A NEW DESIGN AFTER 12 HOURS WORK ON ANOTHER DESIGN.:)