Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Design Issue when FPGA is configured from serial flash

Hi, I am using Cyclone III FPGA to log some data from different analog channels. I have a strange problem with that. when jtag cable is connected everything is fine and working very well. howe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Just to be clear: you don't need to remove jtag debug module or changing buffer size.

You simply have to remove printf calls from your code, especially those displaying lot of data and those called frequently.