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Altera_Forum
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14 years ago

Design Issue when FPGA is configured from serial flash

Hi, I am using Cyclone III FPGA to log some data from different analog channels. I have a strange problem with that. when jtag cable is connected everything is fine and working very well. howe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi guys, many thanks for precious ideas. I will go through it and will let you know. I think 2 ideas are making more sense. I have 2 different designs (Master and Slave) and I think the idea that JTAG buffer became full much make more sense. I will try it without using JTAG buffer and see what happens. I also keep the itag connected and It might be ground issues as well. I don't think so lacking of licence cause this problem as I have used the same IPs on many previous designs. I will let you know guys the outcome. any more ideas will be much much appreciated.