Design Issue when FPGA is configured from serial flash

Are you sure you are not using other unlicensed or time limited cores, besides the licensed Nios?

With "jtag connected" do you mean:

1- simple cable connection

2- use jtag uart terminal

3- load the application in debug mode

Any of these can have a different explanation:

1- grounding or signal integrity problems

2- your application sends debug data through jtag uart: when the buffer fills up, this introduces some excessive delays which are fatal for your application

3- some part of the code behaves differently when compiled in release mode

I guess your situation is nr.2. I had a similar problem, although in my case it caused only an application slowdown during the execution of some tasks.