Design a ram in fpga

Answer1: Designing RAM in an FPGA / CPLD is pretty straightforward as each bit (generally) costs 1 LE. Advantages are that it's a) fast and b) available to other designs other than altera. For instance, this is how you'd create an 8x8 RAM in verilog:

reg [7:0] ram [0:7];

You'd still need to write the interface (clk, we, output wires) but that's basically it. Note that this will take up 8x8=64 LE's, so it's not very efficient. A MAX2-240 would only be able to implement around 200 (if that) bits, which is the main disadvantage of doing it this way. Unfortunately, most CPLD's don't have block-ram so it's the only way to handle it.

Answer2: Yes, you can create RAM in a CPLD but it'd kill your LE count. Most FPGA's have block-ram, which is dedicated memory for this kind of stuff. It's generally registered and FAST. The IP megawizard allows you to create a whole bunch of different designs, from dual-ported to fifo's to shift-registers. The amount of RAM you can implement depends on the device. Generally, the more memory you want, the more expensive the FPGA.

In short, if you want a large amount of RAM in your design, you'll need external memory.

-Mux