Forum Discussion
4 Replies
- MEIYAN_L_Intel
Frequent Contributor
Hi,
This issue seems like due to SGDMA to MSGDMA migration. Intel is recommending the MSGDMA. Please check this document:
https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf (page 297) First line. This change applied also to the TSE, the drivers expect to work with msgdma not sgdma.
Could you try to change from the sgdma to msgdma in your .qsys file?
For your information, there is an example for Nios II Simple Socket Server Ethernet in Quartus Prime Standard v17.1.1: https://fpgacloud.intel.com/devstore/platform/17.1std.1/Standard/nios-ii-simple-socket-server-ethernet-example/,
Also, there is an forum community discuss about this problem, you can see the detail in link below:
https://forums.intel.com/s/question/0D50P00003yyTe9SAE/nios-simple-socket-sever-template-cant-compile
Thanks
- APaga1
New Contributor
I will try changing from the sgdma to msgdma in the .qsys file. The example for Nios II Simple Socket Server Ethernet in Quartus Prime Standard v17.1.1 is for the MAX 10 board. My exploration is limited to Cyclone GT V. Thank you for your reply.
- APaga1
New Contributor
Hello MeiYanL!! By looking at the MAX 10 solution, I've found that the sgdma is being used there in its version 17.1. Can you please elaborate what changes are you suggesting to make by going from the sgdma to msgdma in the .qsys file?
- MEIYAN_L_Intel
Frequent Contributor
Hi,
Could you try to replace the SGDMA controllers with Modular Scatter-Gather DMA ip in .qsys file?
Thanks