Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Demultiplexer with latched value

I am using a demultiplexer with six output registers. The code is pretty simple. process(X,sel) begin case sel is when "000"=> A <=X; when "001" => B <=X; when "01...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

parrado wrote:

--- Quote Start ---

your VHDL code must assign every signal in order to avoid parasite latches

--- Quote End ---

It does not have to. As I wrote , I needed to retain the values on each itteration of next register being sent to output.

that is why , i could not issue statements such as 

B<=(others=>'0');

It would reset tha value of corresponding output pins to zero, which I don't want.

Thanks