Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDemultiplexer with latched value
I am using a demultiplexer with six output registers. The code is pretty simple. process(X,sel)
begin
case sel is
when "000"=>
A <=X;
when "001" =>
B <=X;
when "01...
Altera_ForumHonored Contributor
Honored Contributorparrado wrote:
--- Quote Start --- your VHDL code must assign every signal in order to avoid parasite latches --- Quote End --- It does not have to. As I wrote , I needed to retain the values on each itteration of next register being sent to output. that is why , i could not issue statements such asB<=(others=>'0');
