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Altera_Forum
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16 years ago

Demultiplexer with latched value

I am using a demultiplexer with six output registers. The code is pretty simple. process(X,sel) begin case sel is when "000"=> A <=X; when "001" => B <=X; when "01...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

In fact, demultiplexers aren't often used. Instead, a decoder providing clock-enable signals is preferred.

Nevertheless, your VHDL code must assign every signal in order to avoid parasite latches. 


process(X,sel)
  begin
  case sel is
   when "000"=> 
    A<=X; 
    B<=(others=>'0');
    C<=(others=>'0');
    D<=(others=>'0');
    E<=(others=>'0');
    F<=(others=>'0');
   when "001" => 
    A<=(others=>'0');
    B<=X;     
    C<=(others=>'0');
    D<=(others=>'0');
    E<=(others=>'0');
    F<=(others=>'0');
   when "010" =>
    A<=(others=>'0');
    B<=(others=>'0');
    C<=X;         
    D<=(others=>'0');
    E<=(others=>'0');
    F<=(others=>'0');
   when "011" =>
    A<=(others=>'0');
    B<=(others=>'0');
    C<=(others=>'0');
    D<=X;             
    E<=(others=>'0');
    F<=(others=>'0');
   when "100" =>
    A<=(others=>'0');
    B<=(others=>'0');
    C<=(others=>'0');
    D<=(others=>'0');
    E<=X;                 
    F<=(others=>'0');
   when "101" =>
    A<=(others=>'0');
    B<=(others=>'0');
    C<=(others=>'0');
    D<=(others=>'0');    
    E<=(others=>'0');
    F<=X;                 
end case;
end process;