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Altera_Forum
Honored Contributor
10 years agoDelaying output of a module to close timing
I've created a module where two numbers are multiplied and the output is provided in a number of clock cycles. However, the output of the module (pdt1_out) is failing timing in that the setup slack ...
Altera_Forum
Honored Contributor
10 years agoThanks, kaz. Yes, that sums up nicely what I've also found regarding the use of multicycle paths for this particular design.