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Altera_Forum
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9 years ago

Delaying output of a module to close timing

I've created a module where two numbers are multiplied and the output is provided in a number of clock cycles. However, the output of the module (pdt1_out) is failing timing in that the setup slack ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thanks, kaz. My intention was to have Quartus automatically infer a pipeline multiplier from the HDL code, but I will try the megawizard instance first. I will reply to this thread when I've managed to pipeline the multiplier using the IP.