delayed pulse generator

You can't initialize an input as in:

reg[11:0] Start=0;

reg[12:0] Stop=0;

reg[11:0] StartREF=10;

reg[12:0] StopREF=4700;

You just need an enabled counter.

The counter starts counting the clock cycles when Start goes to '1'

when the counter reaches the delay value (depending on the required delay) then outPulse is asserted.

module GateGENERATORASSER(clk,start,outPulse,delay,reset);

input reset,clk,start

input [7:0] delay; // Maximum 255 clock cycles of delay

output outPulse;

reg [7:0] count;

always @(posedge clk)

begin

if (reset)

count<=8'h00

else

if (start)

count<=count+1;

else

count<=0;

end

assign outPulse= (count>delay) ? 1'b1 : 1'b0;

endmodule

This leaves with a precision that is no lower than the clock period.

And works if start doesn't do strange things.