Altera_Forum
Honored Contributor
Honored Contributordelay
when doing an fpga synthesis with vhdl,what s the most appropriate way of delaying an assignment of a pin;that is signal a : std_logic; a <= '1' after 100 ns; like this ?
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Altera_ForumHonored Contributor
Honored ContributorHi,
My approach would be to design a counter which will give you approximately the same delay as you require in your design. The VHDL code looks like below: --------------------------------------------- process(clk,reset) begin if reset = '1' then count <= 0; elsif rising_edge(clk) then if count < 200 then count <= count + 1; else count <= count; end if; end process; a<= '1' when count = 200 else '0'; ----------------------------------------- I put the 'count' value as 200 as an example. You need to calculate the count value depending on your 'clock' speed. BPR
