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Altera_Forum
Honored Contributor
Honored Contributordelay generation problem
hi, i have done a vhdl project with quartus and call it with nios, I don't have good result do to a delay generation. please how can i repair my work and have this result after this delay?? ...
Altera_ForumHonored Contributor
Honored ContributorIt depends on how you made your component. Show us your code and it will be easier to help you.
