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Altera_Forum's avatar
Altera_Forum
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13 years ago

delay generation problem

hi, i have done a vhdl project with quartus and call it with nios, I don't have good result do to a delay generation. please how can i repair my work and have this result after this delay?? ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Your problem description isn't very clear. If your VHDL component needs some time to process a request, you can have a status register with a "busy" or a "done" flag to tell the software to wait.