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Altera_Forum's avatar
Altera_Forum
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17 years ago

delay for a Sinusoid

I am using an FPGA kit for controlling my power electronic converter. To implement the PLL, I have to give a delay of .005s to a signal whose frequency may range from 20 to 70 Hz. The input is given ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

According to your original post, you won't require taps with your FIFO. In my example cnt_5ms is simply an integer constant, defined above in the code. But you can calculate it from clock frequency and time delay in the code, e.g. 

CONSTANT CLK_PWM_kHz : INTEGER = 40;
CONSTANT DELAY_ms5 : INTEGER = 5;
CONSTANT CNT_5MS : INTEGER = CLK_PWM_kHz*DELAY_ms5;

You may want to read the respective Verilog syntax from a manual or text book.