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Altera_Forum
Honored Contributor
17 years agodelay for a Sinusoid
I am using an FPGA kit for controlling my power electronic converter. To implement the PLL, I have to give a delay of .005s to a signal whose frequency may range from 20 to 70 Hz. The input is given ...
Altera_Forum
Honored Contributor
17 years agoHello FvM,
Thank you very much for your reply.In the code you had mentioned earlier, you had given tap distance in terms of time.But in MegaWizard Plug-in manager, how can I give that? My .v file corresponding to altshift_taps MegaFunction is given below. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module altshift_taps3 ( clock, shiftin, shiftout, taps); input clock; input [11:0] shiftin; output [11:0] shiftout; output [143:0] taps; wire [143:0] sub_wire0; wire [11:0] sub_wire1; wire [143:0] taps = sub_wire0[143:0]; wire [11:0] shiftout = sub_wire1[11:0]; altshift_taps altshift_taps_component ( .clock (clock), .shiftin (shiftin), .taps (sub_wire0), .shiftout (sub_wire1), .aclr (1'b0), .clken (1'b1)); defparam altshift_taps_component.lpm_hint = "RAM_BLOCK_TYPE=M512", altshift_taps_component.lpm_type = "altshift_taps", altshift_taps_component.number_of_taps = 12, altshift_taps_component.tap_distance = 100, altshift_taps_component.width = 12; Can I change this code to get tap distance mentioned in terms of time?