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Altera_Forum's avatar
Altera_Forum
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17 years ago

delay for a Sinusoid

I am using an FPGA kit for controlling my power electronic converter. To implement the PLL, I have to give a delay of .005s to a signal whose frequency may range from 20 to 70 Hz. The input is given ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

For either digitized analog or digital signal, you can use altshift_taps MegaFunction, as in the below example. 


-- CONSTANT CNT_5MS : INTEGER := 500;
  in_beta_delay : altshift_taps
  GENERIC MAP (
    lpm_type => "altshift_taps",
    number_of_taps => 1,
    tap_distance => CNT_5MS,
    width => 16
  )
  PORT MAP (
    clken => phase_pwm_s,
    clock => clk40,
    shiftin => u_Nalpha,
    shiftout => U_Nbeta
  );