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Altera_Forum's avatar
Altera_Forum
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17 years ago

delay for a Sinusoid

I am using an FPGA kit for controlling my power electronic converter. To implement the PLL, I have to give a delay of .005s to a signal whose frequency may range from 20 to 70 Hz. The input is given ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You don't state whether the input is a digital signal, but let's assume it is

(i.e., a square-wave at FPGA-compatible levels)

- Instantiate a 100-bit shift-register clocked at 20KHz. Your signal is the input, and the output is the same, delayed by 50uSec*100= .005s

Wade Hassler