Delay Fault test on 74 series chips problem encountered

Cyclone II doesn't specify an explicite maximum core clock frequency, but numbers above 400 MHz won't leave much margin for logic between register. Set up at least a classical timing analyzer for your design, specifying the 50 MHz input clock, and see the 4-Bit counter (74161) failing setup time by 0.82 ns. In other words, it can run at 350 MHz maximum. There may be more issues with yet unconstrained external signals, however, the simple test shows, that you have to run the design at lower speed or reduce the fast part to more basic operations. The probably best solution is to read the pattern from DUT by a DDR register clocked at 400 MHz, giving you 1.25 ns timing resolution.