delay error in Model_sim

Hi. I have a problem in simulation.

I made a code and It has no error while compiling.

but When i simulated the code in model sim..

It has one delay time. so the output was pushed one pulse.

What's the problem. and how can I fix it?

below is the simulation error image.. below site you can see image.( I can't upload my image... in here!! and if image is so small , then

download and see.. then you can see big image.

Thanks!

http://image.kilho.net/?pk=982125

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY comp is

PORT(

a,b : IN std_logic_vector(1 downto 0);

agb, alb, aeb : OUT std_logic);

END comp;

ARCHITECTURE arc of comp is

SIGNAL result : std_logic_vector(2 downto 0);

BEGIN

PROCESS(a,b)

BEGIN

IF a<b then

result <= "001";

ELSIF a=b then

result <= "010";

ELSIF a>b then

result <= "100";

ELSE

result <= "000";

END IF;

agb <= result(2);

aeb <= result(1);

alb <= result(0);

END PROCESS;

END arc;