Delay chain design?

Hi,

What you have read is true about asynchronous design methodology which is not the practice in FPGAs. FPGAs are designed for synchronous RTL approach. The FPGA logic fabric is too slow for femtosec counting.

FPGA fabric registers cannot run in speeds beyond say 400MHz, in fact I once tried wiring (just wiring) 800MHz signal through and it was corrupted.

So no matter what restrictions you make on LEs, it is not going to help.

At the end you need a time reference to suit your requirement in gigahertz.

You may consider using the serdes (in effect a fast asic part of FPGA)

but for 1 sec pulse you need plenty of work before fpga. For example you can toggle your pule into 0101 pattern while sending another regular idle pattern then you can let serdes detect the start and end of 0101.. but I guess this is too harsh to be practical.