define base types when using enum

Did you notice this comment in the Altera Software Handbook about System Verilog state machine coding style?

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In Quartus II integrated synthesis, the enumerated type that defines the states for the state machine must be of an unsigned integer type as in Example 10–52. If you do not specify the enumerated type as int unsigned, a signed int type is used by default. In this case, the Quartus II integrated synthesis synthesizes the design, but does not infer or optimize the logic as a state machine.

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Suggested definition is:

enum int unsigned { S0 = 0, S1 = 2, S2 = 4, S3 = 8 } state, next_state;