Forum Discussion
New ContributorDedicated SERDES usage for ADC LTC2387-18 with Cyclone V?
Hi Vadim
I hope I understand your situation correctly.
Yes, the ALTLVDS_RX is tied with a PLL. If your design has limitation towards the PLL lock time on the spec, then you have to create logics to implement the receiver.
Unfortunately we don't have sample reference design for this logic creation. For recommendation, we can make use of shift register and parallel register to construct the LVDS receiver.
We shall always refer to "Design Guidelines" mentioned in the doc below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc/cyc_c51009.pdf
Thanks.
Eng Wei
Frequent ContributorHi Vadim
I hope I understand your situation correctly.
Yes, the ALTLVDS_RX is tied with a PLL. If your design has limitation towards the PLL lock time on the spec, then you have to create logics to implement the receiver.
Unfortunately we don't have sample reference design for this logic creation. For recommendation, we can make use of shift register and parallel register to construct the LVDS receiver.
We shall always refer to "Design Guidelines" mentioned in the doc below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc/cyc_c51009.pdf
Thanks.
Eng Wei
New ContributorHi Eng Wei!
Thank you very much for your answer.
Vadim
- EngWei_O_Intel
Hi Vadim
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei
