Forum Discussion
New ContributorDedicated SERDES usage for ADC LTC2387-18 with Cyclone V?
Hi Vadim
I hope I understand your situation correctly.
Yes, the ALTLVDS_RX is tied with a PLL. If your design has limitation towards the PLL lock time on the spec, then you have to create logics to implement the receiver.
Unfortunately we don't have sample reference design for this logic creation. For recommendation, we can make use of shift register and parallel register to construct the LVDS receiver.
We shall always refer to "Design Guidelines" mentioned in the doc below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc/cyc_c51009.pdf
Thanks.
Eng Wei
Frequent ContributorHi Vadim
I hope I understand your situation correctly.
Yes, the ALTLVDS_RX is tied with a PLL. If your design has limitation towards the PLL lock time on the spec, then you have to create logics to implement the receiver.
Unfortunately we don't have sample reference design for this logic creation. For recommendation, we can make use of shift register and parallel register to construct the LVDS receiver.
We shall always refer to "Design Guidelines" mentioned in the doc below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc/cyc_c51009.pdf
Thanks.
Eng Wei
ContributorHi all!
Well, in case the PLL is tied with ALTLVDS_RX core, I suppose that maybe we could use pfdena signal for locking the DCO and so on, but in general we should create receiver logic from LEs.
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Ivan
