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VOS's avatar
VOS
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5 years ago
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Dedicated SERDES usage for ADC LTC2387-18 with Cyclone V?

Hi, I plan to use Cyclone V with ADC LTC2387-18 (15 Msps, 18 bit). Timing diagram of ADC’s digital interface is shown below. CNV and CLK are generated from FPGA (CNV is planned to be l...
  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    5 years ago

    Hi Vadim

    I hope I understand your situation correctly.

    Yes, the ALTLVDS_RX is tied with a PLL. If your design has limitation towards the PLL lock time on the spec, then you have to create logics to implement the receiver.

    Unfortunately we don't have sample reference design for this logic creation. For recommendation, we can make use of shift register and parallel register to construct the LVDS receiver.

    We shall always refer to "Design Guidelines" mentioned in the doc below:

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc/cyc_c51009.pdf

    Thanks.

    Eng Wei

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Thanks Vadim for your inquiry. Allow me some time to go through your design question and get back to you.

Thanks.

Eng Wei

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi Vadim

    I hope I understand your situation correctly.

    Yes, the ALTLVDS_RX is tied with a PLL. If your design has limitation towards the PLL lock time on the spec, then you have to create logics to implement the receiver.

    Unfortunately we don't have sample reference design for this logic creation. For recommendation, we can make use of shift register and parallel register to construct the LVDS receiver.

    We shall always refer to "Design Guidelines" mentioned in the doc below:

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc/cyc_c51009.pdf

    Thanks.

    Eng Wei

    • IDeyn's avatar
      IDeyn
      Icon for Contributor rankContributor
      5 years ago

      Hi all!

      Well, in case the PLL is tied with ALTLVDS_RX core, I suppose that maybe we could use pfdena signal for locking the DCO and so on, but in general we should create receiver logic from LEs.

      ----

      Ivan

    • VOS's avatar
      VOS
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi Eng Wei!

      Thank you very much for your answer.

      Vadim

      • EngWei_O_Intel's avatar
        EngWei_O_Intel
        Icon for Frequent Contributor rankFrequent Contributor
        5 years ago

        Hi Vadim

        I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

        Eng Wei