Decimation or re-sampling filter

Look at the CIC Users Guide. With such a high decimation ratio, you'd probably:

1) Multiply with an NCO signal to mix the signal to baseband

2) Run the complex-valued baseband signal through a decimating CIC filter

3) Run the CIC output through a band-shape correction filter, possibly a half-band filter with decimate by 2.

Its impossible to figure out the resources, without also knowing the dynamic range requirements of your application, i.e., how many bits you need and the out-of-band rejection you need from your filters. You pretty much have design the filters, place-and-route, and then decide whether to select an appropriate sized FPGA, or to further optimize to reduce the logic usage.

The handbooks for the IP have some resource estimates. You could start with that, and then create a few designs using Quartus.

Your initial sample rate is quite slow, and your over-sampling ratio is high. I suspect you'll have no issue using the Cyclone series devices.

Start with a large Cyclone IV, and then work your way to the cheaper devices. The cheaper you go, the fewer features you have, eg., less feature-full DSP blocks. You'll have to 'play' with a few designs to see what works for your application.

Note that there are probably ASICs that already do what you want - TI comes to mind. Before deciding that an FPGA is your low-cost solution, check the competition. You might find that a MAX II + SDR ASIC is the lowest cost.

Cheers,

Dave