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Altera_Forum
Honored Contributor
Honored ContributorDebugging interface issue on FPGA
Hi, I have a data processing module that takes only clock and reset as input and generate an expected sequence of data. When this design is tested in stand-alone mode, it works fine. But when i...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The data generated is sent off the chip to other device. The data is passed through a DAC and observed on oscilloscope. In stand-alone mode, the output on oscilloscope is repetitive with a fixed pattern. When integrated in bigger system, the output is still repetitive but the pattern is wrong. --- Quote End --- And what does your Modelsim simulation of both systems show you? Is the design constrained for timing correctly in both cases? --- Quote Start --- I made sure that my module takes only clock and reset as input when integrated in bigger system to isolated data dependency problem. This integration of bigger system is done by a different team at different location and I do not have access to the board. --- Quote End --- You need to look at the simulation output from both the small system and the large system. You should do this for both pre-synthesis and post-synthesis. Cheers, Dave
