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I have a data processing module that takes only clock and reset as input and generate an expected sequence of data.
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This is a pretty vague description. Is this data generated and used by on-chip logic, or does it go off chip to some other devices?
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When this design is tested in stand-alone mode, it works fine. But when integrated in a larger system the output is messed up.
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'Works fine', 'messed up'; again pretty vague.
What have you tried, eg., have you created a simulation of the design and checked that it passes your tests in stand-alone mode and integrated into the system, have you looked at the data with SignalTapII, what is the difference when data is Ok versus 'messed up'? Can you use data that has an obvious pattern, eg. a counter or a PRBS sequence?
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I looked at synthesis warnings to make sure none of the data processing module signals are trimmed. STA report has no timing violations. The clock and reset going to data processing module are clean.
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Is there only one clock, or are you using the PLLs to generate more clocks?
Cheers,
Dave
Honored Contributor
