Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

DE5-NET JTAG Configuration Problem

Hi all, I tried to program the Stratix V FPGA on the DE5-NET board through the UBS Blaster cable. Each time, the programmer goes up to somewhere between 95% - 98% and fail. The error i get is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I experienced an identical problem when I received a DE5-Net from a preproduction batch that uses an engineering sample (ES) FPGA. You can tell if you have one of these by removing the fan and seeing if the part number printed on the FPGA ends in ES.

If it does, you will need to change the target device to 5SGXEA7N2F45C2ES in all projects, and recompile to demonstration projects if you want to use them.

Also note that there is a serious bug in the flash programmer circuitry in Stratix V ES parts. If the flash programmer is used at all (e.g to load the demo bitstream when a board is powered on), then the FPGA goes into secure mode and won't accept any further programming commands (e.g from the USB blaster). To work around this Terasic have deliberately broken the flash programmer (so that it can't program the FPGA and hence it still accepts programming commands after power on) by incorrectly setting the MSEL dip switches near to the MAX II. If you have an ES FPGA then these will have to be set to DOWN-UP-UP-DOWN-UP-UP.