Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

DE5-NET JTAG Configuration Problem

Hi all, I tried to program the Stratix V FPGA on the DE5-NET board through the UBS Blaster cable. Each time, the programmer goes up to somewhere between 95% - 98% and fail. The error i get is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

You can turn down the USB-Blaster II JTAG clock speed with this command:

jtagconfig --setparam <cable name> JtagClock <speed>

The cable can't do every cable speed but it won't run faster than you specify, use --getparam to read the current value.

The fastest three speeds it can run at 6M, 16M and 24M (the default).