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Altera_Forum
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12 years ago

DE5-NET JTAG Configuration Problem

Hi all, I tried to program the Stratix V FPGA on the DE5-NET board through the UBS Blaster cable. Each time, the programmer goes up to somewhere between 95% - 98% and fail. The error i get is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The reason it fails at 99% is because the programmer does not have a way to check if the bitstream was OK until it has loaded it all into the FPGA, the check of CONF_DONE happens after all the data has been downloaded.

So you're putting bad data into the FPGA and it's rejecting it. There are two possible reasons for this - either you somehow generated a bad sof/pof file or your data is getting corrupted on the way to the FPGA.

Which sort of USB-Blaster are you using? The on-board one or one plugged into the 10 pin socket on the board?