DE2-70 Verilog SDRAM Controller

1) create a new (empty) Qsys project

2) add the SDRAM Controller and configure it for your device organization and timing

3) connect the clock and reset

4) export the Avalon-MM Slave port and the Conduit for the SDRAM pins

5) generate the system

6) this is the end of using Qsys, forever

7) take the generated file (e.g. <qsys_project_name>/synthesis/submodules/sdram_0.v) and copy it wherever you like, modify it however you like, including removing the Avalon-MM should you care to.

It is a small hurdle to get your hands on what otherwise is a relatively straightforward piece of Verilog (crafted by a Perl script) with correct organization and timing for your devices.

Or, if you're OK with the GPL, check out the OpenCores project; but I'm not sure if that is more or less work as a starting point than the reference design you already found and are hesitant to use.