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Altera_Forum's avatar
Altera_Forum
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12 years ago

DE2-115 SDRAM without NIOS

I'm trying use the SDR SDRAM on the DE2-115 FPGA development board in verilog. I can't use NIOS as the interrupts aren't fast enough for my application. As far as I can tell I have 2 options: ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

I used a single 133.33MHz PLL and raw HDL, that was it!

To sum up what I did:

To initialise:

  • waited over 200µs for the SDRAM to boot up

  • precharged all the banks

  • auto-refreshed 8 times

  • program the mode register (M0-4:0, M5:1, M6-8:0, M9:1)

  • precharge all banks

Then while idling just looped this:

  • auto refresh

  • nop & check for waiting read/write

The problems I encountered were mainly around timing. The tRC, tMRD, latency etc times listed in the datasheet are not all correct. I can't remember exactly which ones were wrong, but some were and I had to go through a lot of trial and error to get it working.

Basically I had to read 90% of the datasheet and then slightly wiggle some of the quoted numbers to get it working as expected.