DE2_115 GPIO High and low voltage

When you set JP6 jumper for VCCIO = 3.3V, then your GPIOs must go from nearly 0 to nearly 3.3V when configured as outputs.

If you actually measure a level around 1.5V then you probably have made some mistake. Anyway, what do you mean with 'seems'? how do you measure it?

I am too lazy to look up page 46. Is this the 40 pin header?

As to measuring, maybe this thread may give some help: http://www.alteraforum.com/forum/showthread.php?t=45973&highlight=

Thanks for replies. Let me say my imagination! FPGA outputs/gpio pins are working digital which means 1 and 0. state 1 means 3.3 Volt and state 0 means 0 volt. Is it correct? 3.3 Volt shows 1 and what voltage would be the border of low state (0)?

What I did: I connect one gpio pin of DE0-Nano to a potentiometer and output of potentiometer to one gpio pin as input of DE2-115.

DE2-115 output is assigned to a LED. by changing potentiometer when voltage became lower than 1.5 the LED turns off. I consider it as low voltage? Cannot be?

Then I searched the DE2-115 manual and it was something about low and high voltage. High voltage could be reasonable but what low voltage means?

This idea came to me because I am doing some AD converting by FPGA. I used to use DE0-Nano to make square waveform like as our real device output waveform and do some feedback loop. This feedback could be like as go to low state after passing specified voltage. Then I realized DE0-Nano output is digital even if it is similar to our device output waveform. Then I tried to see the reaction of FPGA pins when interfacing together.

As last question: It could be crazy but what happens if we input fpga produced square waveform to ADCs? Any idea?

Thanks for your time and helps.