Hi everyone, I am going to use the terasIC High Speed AD/DA daughter card (http://www.terasic.com.tw/cgi-bin/pa...english&no=278 (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=278)) in combination with the DE2-115 board. Unfortunately i have no idea how i can get the values from the selected AD-Channel read out. I wonder how i can get the converted value (14 bit) of an analog signal on the led of DE2? Has anyone a code-example (written in vhdl) which uses the terasic ada card? so perhaps i can get a hint how i can implement the daughter card in my future experiments? Would be very helpful. Thanks

Have you looked through the wealth of information available on the resource CD the accompanies the board? I'd suggest that's a good place to start. This includes specific examples and project templates for the DE2-115 board. I accept you're after VHDL and most of Terasic's support code is in verilog. However, I'm very sure it'll help. The 14-bit values are presented directly, in parallel, across the HSMC connector. So, it's a 'simple' case of assigning those FPGA input signals to the appropriate FPGA LED output pins... Cheers, Alex

Thank you much for reply. I have done some projects with DE0-Nano and it's ADC. That one is different and has a clear guidance by Altera (pins, how data transfer, and ...). Let me explain a simple example, Consider a variable resistor and its output for using as an analog input signal for ADC. When we changes the resistance the voltage changes and of course converted bytes also. This is the first project which I want to do it by this AD/DA board and DE2-115! As I see in the Data_conversition_HSMC_reference_manual I have Channel A and B as SMA inputs. Why two channel? Can I do it by one channel only? And so far I have done this simple vhdl code and pin assignment just to see such a simple analog input in LEDs of DE2-115. But it doesn't work! library ieee; use ieee.std_logic_1164.all; USE IEEE.NUMERIC_STD.ALL; entity test is port( ADA_D : in std_logic_vector (13 downto 0); clk : in std_logic; ADA_DCO: in std_logic; ADA_OE : out std_logic; ADA_OR : in std_logic; ADA_SPI_CS: out std_logic; AD_SCLK : inout std_logic; AD_SDIO : inout std_logic; AIC_BCLK : inout std_logic; AIC_DIN : out std_logic; AIC_DOUT : in std_logic; AIC_LRCIN: inout std_logic; AIC_LRCOUT: inout std_logic; AIC_SPI_CS: out std_logic; AIC_XCLK : out std_logic; CLKIN1 : in std_logic; CLKOUT0: out std_logic; FPGA_CLK_A_N: inout std_logic; FPGA_CLK_A_P: inout std_logic; J1_152: inout std_logic; XT_IN_N : in std_logic; XT_IN_P : in std_logic; bit_out1: out std_logic_vector (13 downto 0) ); end test; architecture behavioral of test is begin process (ADA_D) begin bit_out1 <= ADA_D; end process; end behavioral; bit_out1 is assigned to LEDs to see the voltage changing. I have done the pin assignment according to DE2-115 projects and I think it is fine. I do not know where is the real input? which signal is that one? Am I completely wrong or a part of? Hope you can help me to solve the problem. Thanks

--- Quote Start --- OK - there isn't anything wrong with your code. However, there is a problem if you're trying to do what I think you are - I'm assuming you're trying to connect to the DE2-115 board via the HSMC connector. Right? The ADC connections from the THDB-ADA board aren't connected up to the FPGA on that development board. Perhaps that sounds odd - but they aren't. The pins from the top 'third' of the HSMC connector - where the ADC signals are broken out from the ADA board - aren't taken to the FPGA (with the exception of a few intended for I2C, clock and JTAG related functions - not relevant to the ADA). I note that reference is made to use of the DE2-115 board in the manual for the ADA board but no mention of this limitation. I think that's a little poor. I attach the relevant pages of the schematic for each board for you to consider yourself. However, the ADC signals are also taken to J7, one of the GPIO connectors on the ADA. You may be able to connect it to the DE2-115 board via that. You'll probably need to remove the DE2-115 board's protective perspex cover to do so. Cheers, Alex --- Quote End --- Hi Alex, Could you be more specific on which ADC signals aren't taken to the FPGA ? We'd like to mention that in the user manual, if there's any. When I look at how the HSMC pins from ADA-HSMC are named and oriented, I have to admit it is easy to get confused and lost for them being completely upside down. I guess that's the reason why we change the number order afterwards, so the pins on both ends can be mapped directly. David from Terasic

Hi David, I take your point. Having had another look at the schematics it appears that AD/DA board schematic has flipped the pin order of the HSMC connector vertically. I find this pretty poor given the lack of support Terasic offer in the documentation for the board. Various connector manufacturers omit pin numbering on their connectors and leave it to the user to identify something convenient for them. However, Samtec specify a pin order for this particular connector, a pin order that Terasic have used for the DE2-115 board (and others). So, why flip the pin order for the connector on this board? The problem is made worse still since the orientation of the connector in the schematic appears to be the same as to the DE2-115 board. Combined with the pin order issue and I'd forgive anyone making the same mistake. Keeping in mind that the DE2-115 board uses a 172 pin version of the connector rather than the 192 pin version on the D/B - the pin mapping for the connectors on this particular board combination appears to be: ad/da - de2-115 1 - 159 2 - 160 3 - 157 4 - 158 etc. So, rebk - it looks like I and Terasic have sent you on a bit of a wild-goose chase. I suspect the boards are compatible. Perhaps David (or someone else) from Terasic can provide you with a Quartus project template for the DE2-115 board fitted with the AD/DA board... Cheers, Alex

Hi Guys, Thank you all for clarifications and your time. I have worked with DE0-Nano and its ADC and because of its perfect User Guide there were not big problems and it was more simpler because of having NO HSMC connection. One more point, I am using the AD/DA conversion card and it is different with THDB-ADA. What I have done so far, I have used pin assignment of sample project of terasic for DE2-115 board and AD/DA conversion card. Why I can not use the example project structure for my design because it is totally different with my purpose. In the terasic example they produce 1 Mhz and 10 Mhz sinusoidal signal and then transfer it through AD input to DA input. So far I only need to use AD input for my project to convert Analog signal to Digital and limit it somehow with FPGA. With thanks to Dave for many instructions I have below questions: 1- I have used Terasic example pin assignment for my design, Is it OK? I suppose it is ok because AD input pins are same? Isnt it? 2- There are many other signals which I do not know which one is necessary for a simple AD project like as clk : in std_logic; ADA_DCO : in std_logic; ADA_OE : out std_logic; ADA_OR : in std_logic; ADA_SPI_CS: out std_logic; AD_SCLK : inout std_logic; AD_SDIO : inout std_logic; FPGA_CLK_A_N: inout std_logic; FPGA_CLK_A_P: inout std_logic; but anyway I have assigned them as terasic sample project. 3- Which clock signal should I use? There are many clock signals like as clk, AD_SCLK, FPGA_CLK_A_N, FPGA_CLK_A_P, CLKIN1, CLKOUT0 Some questions maybe seem simple and funny for you guys but it is difficult for me. I am here to learn and hope you help me with your knowledge. Regards

DE2-115 and Terasic High Speed AD/DA daughter card

12 Replies

Altera_Forum
Honored Contributor
10 years ago
Thanks Alex,

Now there is a question about type of input signal. As there is a RF transformer after the input of AD card, What kind of input can I have? Currently I am trying to input a 2V DC input. but the input (SMA input terminal) is shorted. I mean there is no place for ground. My final goal is to input 100 Hz square waveform with duty cycle of only 80 ns. I have attached the AD card input schematic and my desired project with AD and FPGA.
I have an input signal as 2V amplitude, 80 ns, 100 Hz and want to convert it by ADC to digital then I can limit/modify the bites (the input).
Please have a quick look at it and let me know your instructions.

Regardshttps://www.alteraforum.com/forum/attachment.php?attachmentid=10727
multiple-attachments.zip460 KB
Altera_Forum
Honored Contributor
10 years ago
Hi rebk,

The 2V DC signal you're applying isn't going to get through the transformer. AC only I'm afraid. So, don't expect any exciting results from your initial tests.

As already stated there is a 49R9 resistor to ground on the input. So, it's not shorted to ground but it is intended to be driven by something with a 50R source impedance.

As for what input signal is appropriate - you'll need to refer to the Reference Manual for the Data Conversion card. See the 'A/D Converter' section under 'Component Interfaces' on page 2-8.

--- Quote Start ---
I have an input signal as 2V amplitude, 80 ns, 100 Hz...
--- Quote End ---

Do you mean an 80ns pulse every 10ms? That might work. However, you need to be aware that the shape of the signal going into the ADC is going to be somewhat different to the signal you drive in thanks to that transformer.

Cheers,
Alex

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DE2-115 and Terasic High Speed AD/DA daughter card

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