Honored Contributor
Honored ContributorThank you Cris72, but let me understand you correctly...
You mean that I have to have one Tri_state_bridge component with two ports: tri_state_bridge.tristate_master and tri_state_bridge.tristate.slave. The master should be connected to Avalon cpu busses data & instruction, and the slave should be connected to the SRAM model. That makes perfect sense, but...... What I did is I added tri_state_bridge in SOPC and automatically it connected the tri_state_bridge.tristate_slave to the Avalon bus master (Nios II cpu.data.master and cpu.instruction.master ). However, the other tri_state_bridge.master is left without connection, and this gave me an error. Also, how can I build my own SRAM model?
