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What's the point of using 4 clocks instead of a single one with a 4-state process?
Besides the fact this is not synthetizable in fpga (as Fvm already said, a physical flip-flop has a SINGLE clock input), the overall logic flow of your code is wrong, too.
For example, when you have a clk180_in clock edge, I believe you want the code inside "if (clk180_in)" to be executed; but, if mclk_in or pclk_in signal is still high this is not the case, since one of the previous "if" condition is also true.
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Hi Cris72, the reason I m using 4 clocks because I want to achieve 1ns counter resolution.
Ok..i understand the problem now. Thanks for pointing that out.
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