Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

DE2 : GPIO output waveforms

Hi..i am having a problem and don't have any idea how to solve this problem. I had do the simulation using modesim and working fine. However when I download the code to DE2 board with Cyclone II, the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

You didn't post all design files, Ton_Ctrl.v is missing. I looked at sync_ctrl and trig_ctrl units and see that you misunderstand both the Verilog syntax for clocksensitive circuits and the hardware features of FPGA.

A flip-flop like pulse_out1 can have only one clock input. In the below shown always block from sync_ctrl.v, no clock is defined at all. 

always @(posedge mclk_in or posedge pclk_in or posedge clk180_in or posedge clk270_in or negedge rst_in)     
begin 
  if (rst_in == 0)                                
     	pulse_out1 <= 1'b0;
  else if (mclk_in)
      begin        
          if ((trig_in)&&(pw_in) == 1)       
              pulse_out1 <= 1'b1;                  
          else 
              pulse_out1 <= 1'b0;      					
      end
  else if (pclk_in)
      begin        
          if ((trig_in)&&(pw_in) == 1)       
              pulse_out1 <= 1'b1;                  
          else 
              pulse_out1 <= 1'b0;      					
      end
  else if (clk180_in)
      begin        
          if ((trig_in)&&(pw_in) == 1)       
              pulse_out1 <= 1'b1;                  
          else 
              pulse_out1 <= 1'b0;      					
      end
  else if (clk270_in)
      begin        
          if ((trig_in)&&(pw_in) == 1)       
              pulse_out1 <= 1'b1;                  
          else 
              pulse_out1 <= 1'b0;      					
      end 
  else
     pulse_out1 <= 1'b0;        
end